Low noise amplifier circuit with noise cancellation and increased gain

ABSTRACT

A low noise amplifier circuit including a front end voltage sensing and matching amplification circuit, a gain circuit and a combining circuit is disclosed. The front end voltage sensing and matching amplification circuit includes an input and two outputs and provides a matched signal at each output. The gain circuit includes two inputs, each input being respectively coupled to at least one of the two outputs of the front end voltage sensing and matching amplification circuit. The gain circuit further includes two outputs and an output signal is provided at each output of the gain circuit. The combining circuit combines the two output signals of the gain circuit. The combining circuit includes two inputs, each input is respectively coupled to at least one of the two outputs of the gain circuit. The combining circuit further includes an output providing a combined signal.

This application is the National Stage of International Application No.PCT/SG2006/000294, filed on Oct. 4, 2006.

I. FIELD OF THE INVENTION

The present invention relates to the field of low noise amplifiers(LNA), and in particular, to low noise amplifier circuits with noisecancellation and increased gain.

II. BACKGROUND OF THE INVENTION

Wideband and ultra-wideband LNAs have received extensive researchinterests in recent years. A wide range of modern and futurecommunication systems have been proposed that operates over a bandwidthexceeding several GHz, examples of these systems includesoftware-defined radio, ultra-wideband (UWB), and so on. This poses amore stringent requirement on the UWB transceiver, especially for thefront-end LNA, which has to provide an ultra-wide bandwidth withreasonable noise figure and impedance matching.

Traditionally, these types of wideband amplifiers were implemented withbalanced or distributed architectures that were originally used inmicrowave circuit design as described in publication “A 0.5-14-GHz10.6-dB CMOS Cascode Distributed Amplifier”, Liu R. C, et al, 2003Symposium on VLSI Circuits Digest of Technical Papers. However, largearea occupation and high power dissipation of traveling-wave amplifiermake it infeasible for low-power single-chip integration. Lumpedimplementations of UWB LNA were normally achieved by negative feedbackor multi-section LC-network. Meanwhile, inductor peaking technique isoften adopted for bandwidth enhancement. However, the extra passivedevices used for matching purpose increase design complexity and areaoccupation.

Comparing with narrowband LNA designs, severe tradeoffs between noisefigure and source impedance matching exist in wideband LNA. Most ofreported UWB LNA designs are focused on bandwidth enhancement. As aresult, few of them achieve comparable noise performance. A CMOS UWB LNAemploying noise-canceling technique is reported in publication “Abroadband noise-canceling CMOS LNA for 3.1-10.6-GHz UWB receiver”, LiaoC. H. et al, IEEE 2005 Custom Integrated Circuits Conference whereinductive series and shunt peaking techniques are used to extend theeffective bandwidth of noise canceling. Another wide-band LNA designexploiting thermal noise canceling technique is reported in publication“Wide-band CMOS Low-Noise Amplifier Exploiting Thermal Noise Canceling”,Federico Bruccoleri et. al, IEEE Journal of Solid-State Circuits, Vol.39, No. 2, Feb. 2004, where thermal noise of input matching transistorcan be sensed and canceled by the feedforward configurations. Thisavoids the potential instability due to global negative feedbacks.However, the gain performance of such a configuration is often lesssuperior.

There is less freedom in controlling the gain performance of CMOS UWBLNA in prior art devices, especially in the GHz range. Comparing to SiGeBiCMOS where higher gm is available, the gain issue becomes more severewhen it is applied to CMOS devices. Therefore, an objective of thepresent invention is to provide an alternative low noise amplifier withnoise cancellation and increased gain thereby advantageously avoids orreduces some of the above-mentioned drawbacks of prior art devices.

III. SUMMARY OF THE INVENTION

In one embodiment of the invention, a low noise amplifier circuit isprovided including a front end voltage sensing and matchingamplification circuit having an input and two outputs, the front endvoltage sensing and matching amplification circuit providing a matchedsignal at each output. The low noise amplifier circuit further includesa gain circuit having two inputs, each input being respectively coupledto at least one of the two outputs of the front end voltage sensing andmatching amplification circuit, the gain circuit further having twooutputs, an output signal being provided at each output of the gaincircuit. The low noise amplifier circuit further includes a combiningcircuit combining the two output signals of the gain circuit, thecombining circuit having two inputs, each input being respectivelycoupled to at least one of the two outputs of the gain circuit, thecombining circuit further including an output providing a combinedsignal.

In one embodiment of the invention, the gain circuit includes a firstgain enhancement circuit having an input coupled to a first output ofthe front end voltage sensing and matching amplification circuit and anoutput coupled to a first input of the combining circuit. The gaincircuit further includes a second gain enhancement circuit having aninput coupled to a second output of the front end voltage sensing andmatching amplification circuit and an output coupled to a second inputof the combining circuit. The second gain enhancement circuit is coupledto the first gain enhancement circuit. The first gain enhancementcircuit and the second gain enhancement circuit have a common currentbranch and provide two concurrent feedforward paths to the combiningcircuit.

In another embodiment of the invention, the gain circuit furtherincludes a virtual ground circuit connected between the first gainenhancement circuit and the second gain enhancement circuit on one sideand to a reference potential on the other side. The reference potentialmay be a ground connection. The virtual ground circuit includes acapacitive element, a first terminal of which being connected to thefirst gain enhancement circuit and the second gain enhancement circuitand a second terminal of which being connected to the referencepotential.

In a further embodiment of the invention, the low noise amplifierfurther includes an alternating current coupling circuit having an inputcoupled to the first output of the front end voltage sensing andmatching amplification circuit and an output coupled to the input of thefirst gain enhancement circuit. The alternating current coupling circuitfurther includes a capacitive element and a resistive element.

In another embodiment of the invention, the low noise amplifier furtherincludes a current enhancement circuit connected between the first gainenhancement circuit and the second gain enhancement circuit, the currentenhancement circuit providing additional current to the second gainenhancement circuit. The current enhancement circuit further beingconnected to the virtual ground circuit. The current enhancement circuitincludes a resistive element.

In another embodiment of the invention, the front end voltage sensingand matching amplification circuit includes a voltage sensing amplifiercircuit and a matching amplifier circuit.

In another embodiment of the invention, the voltage sensing amplifiercircuit includes an input and an output, the output being coupled to aninput of the second gain enhancement circuit. The voltage sensingamplifier circuit includes a feedback resistor and a source resistorsensing the voltage applied to the input of the voltage sensingamplifier circuit.

In another embodiment of the invention, the matching amplifier circuitincludes an input and an output being coupled to the first gainenhancement circuit. The matching amplifier circuit includes thefeedback resistor, a resistive element and a transistor providing thesource resistor matching.

In another embodiment of the invention, the first gain enhancementcircuit includes a transistor and a resistive element. The second gainenhancement circuit includes a transistor and a resistive element.

In another embodiment of the invention, the combining circuit includestwo serially coupled transistors.

In another embodiment of the invention, the low noise amplifier furtherincludes a first capacitor peaking circuit connected between the firstgain enhancement circuit and the second gain enhancement circuit. Thefirst capacitor peaking circuit includes a capacitive element and aresistive element.

In another embodiment of the invention, the low noise amplifier furtherincludes a second capacitor peaking circuit connected between the secondgain enhancement circuit and a reference potential. The referencepotential may be a ground connection. The second capacitor peakingcircuit includes a capacitive element and a resistive element.

In another embodiment of the invention, the low noise amplifier furtherincludes a third capacitor peaking circuit connected between thecombining circuit and a reference potential. The reference potential maybe a ground connection. The third capacitor peaking circuit includes acapacitive element and a resistive element.

In one embodiment of the invention, a gain circuit in a low noiseamplifier is provided. The gain circuit includes a first gainenhancement circuit having an input coupled to a first output of a frontend voltage sensing and matching amplification circuit and having anoutput. The gain circuit further includes a second gain enhancementcircuit coupled to the first gain enhancement circuit and having aninput coupled to a second output of the front end voltage sensing andmatching amplification circuit and having an output. The gain circuitfurther includes a virtual ground circuit connected between the firstgain enhancement circuit and the second gain enhancement circuit on oneside and a reference potential on the other side. The referencepotential may be a ground connection. The first gain enhancement circuitand the second gain enhancement circuit have a common current branch andare being configured to provide two concurrent feedforward paths to acombining circuit.

The following figures illustrate various exemplary embodiments of thepresent invention. However, it should be noted that the presentinvention is not limited to the exemplary embodiments illustrated in thefollowing figures.

IV. BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block level representation of the architecture of the lownoise amplifier circuit according to an embodiment of the presentinvention;

FIG. 2 shows a circuit level representation of the architecture of thelow noise amplifier circuit according to an embodiment of the presentinvention;

FIG. 3 shows a graph of simulated performance of scattering parameters(S11, S21) versus frequency (F) and noise figure (NF) versus frequency(F) based on the architecture of the low noise amplifier according to anembodiment of the present invention;

FIG. 4 shows a schematic of a capacitive-peaking common-source circuit;

FIG. 5 shows a circuit level representation of the architecture of thelow noise amplifier circuit with capacitive-peaking common-sourcecircuit according to an embodiment of the present invention;

FIG. 6A shows a graph of simulated performance of voltage gain (Av)versus frequency (F) of a common-source circuit with capacitive-peakingbased on calculated gain according to an embodiment of the presentinvention and FIG. 6B shows a graph of simulated performance of voltagegain (Av) versus frequency (F) of a common-source circuit with andwithout capacitive-peaking based on actual circuit implementationaccording to an embodiment of the present invention;

FIG. 7 shows a die microphotograph of a fabricated low noise amplifierchip according to an embodiment of the present invention;

FIG. 8 shows a graph of simulated and measured performance of power gain(S₂₁) and input return loss (S₁₁) versus frequency according to anembodiment of the present invention;

FIG. 9 shows a graph of simulated and measured performance of noisefigure versus frequency according to an embodiment of the presentinvention;

V. DETAILED DESCRIPTION OF THE INVENTION

Exemplary embodiments of a low noise amplifier with noise cancellationand increased gain are described in details below with reference to theaccompanying figures. In addition, the exemplary embodiments describedbelow can be modified in various aspects without changing the essence ofthe invention.

FIG. 1 shows a block level representation of the architecture of the lownoise amplifier circuit according to an embodiment of the presentinvention. The architecture of the low noise amplifier comprises of thefollowing functional blocks, namely a matching amplifier circuit 100, avoltage sensing circuit 102, an alternating current (AC) couplingcircuit 104, a first gain enhancement circuit 106, a second gainenhancement circuit 108, a virtual ground circuit 110, a currentenhancement circuit 112 and a combining circuit 114. Signal from aninput source 116 is delivered to an input of the voltage sensingamplifier circuit 102 and an input of the matching amplifier circuit 100respectively. The voltage sensing amplifier circuit 102 senses thesignal and noise voltages across the input source 116. The voltagesensing amplifier circuit 102 comprises of a source resistor (Rs) and afeedback resistor (Rf). The matching amplifier circuit 100 providesmatching to the source impedance (Rs) of the input source 116. Thematching amplifier circuit 100 comprises of a resistor (R1), a feedbackresistor (Rf) and a transistor (M1). The matching amplifier circuit 100and the voltage sensing amplifier circuit 102 forms a front end voltagesensing and matching amplification circuit 118 where signal and noisesensing and matching amplification are performed in a single circuithaving an input and two outputs. The output signal from the matchingamplifier circuit 100 is delivered to an input of the AC couplingcircuit 104. The AC coupling circuit 104 comprises of a resistiveelement (R7) and a capacitive element (C1). The output signal of the ACcoupling circuit 104 is delivered to an input of the first gainenhancement circuit 106. The first gain enhancement circuit 106comprises of a resistor (R3) and a transistor (M3). The output signal ofthe voltage sensing amplifier circuit 102 is delivered to an input ofthe second gain enhancement circuit 108. The second gain enhancementcircuit 108 is coupled to the first gain enhancement circuit 106 andcomprises of a resistor (R2) and a transistor (M2). The virtual groundcircuit 110 or a decoupling capacitor is configured between the firstgain enhancement circuit 106 and the second gain enhancement circuit 108for creating a ground node at high frequency. The virtual ground circuit110 comprises of a capacitor (C2). The current enhancement circuit 112is configured between the first gain enhancement circuit 106 and thesecond gain enhancement circuit 108 and is in connection with thevirtual ground circuit 110. The current enhancement circuit 112 providesextra current to the second gain enhancement circuit 108 and comprises aresistor (R8). The output signal from the first gain enhancement circuit106 and the output signal from the second gain enhancement circuit 108are combined in the combining circuit 114 to produce an output signal120. The first gain enhancement circuit 106, the second gain enhancementcircuit 108 and the virtual ground circuit 110 forms a gain circuitpositioned between the front end voltage sensing and matchingamplification circuit 118 and the combining circuit 114 to provide gainenhancement to the low noise amplifier circuit. The gain circuitreceives two input signals and generates two output signals which aresubsequently combined by the combining circuit 114.

FIG. 2 shows a circuit level representation of the architecture of thelow noise amplifier circuit according to an embodiment of the presentinvention. The front end voltage sensing and matching amplificationcircuit comprising of a voltage sensing amplifier circuit and a matchingamplifier circuit. The voltage sensing amplifier circuit comprises ofthe source resistor (Rs) of the input source and the feedback resistor(Rf). The feedback resistor (Rf) comprises two ends, a first end coupledto the source resistor (Rs) and a second end coupled to the matchingamplifier circuit. The matching amplifier circuit comprises a resistor(R1), the feedback resistor (Rf) and a transistor (M1). The transistor(M1) is an NMOS comprising of a source terminal, a gate terminal and adrain terminal. The source terminal of the transistor (M1) is coupled toa ground connection, the gate terminal of the transistor (M1) is coupledto the first end of the feedback resistor (Rf) and the drain terminal ofthe transistor (M1) is coupled to the second end of the feedbackresistor (Rf), the resistor (R1) and an AC coupling circuit. Theresistor (R1) comprises two ends, a first end coupled to the drainterminal of the transistor (M1), the second end of the feedback resistor(Rf) and the AC coupling circuit and a second end is coupled to a powersupply. The AC coupling circuit comprises a capacitor (C1) and aresistor (R7). The capacitor (C1) comprises two ends, a first end iscoupled to the first end of the resistor (R1), the second end of thefeedback resistor (Rf) and the drain terminal of the transistor (M1) anda second end is coupled to the resistive element (R7). The resistor (R7)comprises two ends, a first end coupled to the second end of thecapacitor (C1) and a first gain enhancement circuit and a second endcoupled to a power supply. The first gain enhancement circuit comprisesa transistor (M3) and a resistor (R3). The transistor (M3) is a NMOScomprising of a source terminal, a gate terminal and a drain terminal.The source terminal of the transistor (M3) is coupled to a second gainenhancement circuit, a virtual ground circuit and a current enhancementcircuit, the gate terminal is coupled to the second end of the capacitor(C1) and the first end of the resistor (R7) and the drain terminal iscoupled to the resistor (R3) and a combining circuit. The resistor (R3)comprises two ends, a first end coupled to the drain terminal of thetransistor (M3) and the combining circuit and a second end coupled tothe power supply. The second gain enhancement circuit shares the samedirect current (DC) branch with the first gain enhancement circuit (asshown by the arrow between transistor (M3) and resistor (R2)). Thesecond gain enhancement circuit comprises a transistor (M2) and aresistor (R2). The transistor (M2) is a NMOS comprising of a sourceterminal, a gate terminal and a drain terminal. The source terminal ofthe transistor (M2) is coupled to the ground connection, the gateterminal is coupled to the first end of the feedback resistor (Rf) andthe gate terminal of the transistor (M1) and the drain terminal iscoupled to the resistor (R2) and the combining circuit. The resistor(R2) comprises two ends, a first end coupled to the drain terminal ofthe transistor (M2) and the combining circuit and a second end coupledto the first gain enhancement circuit, the virtual ground circuit andthe current enhancement circuit. The virtual ground circuit comprises alarge decoupling capacitor (C2) that creates a ground node at highfrequency. The capacitor (C2) comprises two ends, a first end coupled tothe second end of the resistor (R2), source terminal of the transistor(M3) and a first end of a resistor (R8) and a second end is coupled to aground connection. The current enhancement circuit comprises theresistor (R8). The second end of the resistor (R8) is connected to thepower supply. The combining circuit comprises two transistors (M4, M5).Both the transistors (M4, M5) are NMOS comprising of a source terminal,a gate terminal and a drain terminal respectively. The source terminalof the transistor (M4) is coupled to the ground connection, the gateterminal is coupled to the drain terminal of the transistor (M2) and thefirst end of the resistor (R2) and the drain terminal is coupled tosource of the transistor (M5), giving rise to the output signal. Thegate terminal of the transistor (M5) is coupled to the drain terminal ofthe transistor (M3) and the first end of the resistor (R3) and the drainterminal is coupled to the power supply.

In FIG. 2, the gain circuit comprising of the first gain enhancementcircuit, the second gain enhancement circuit and the virtual groundcircuit provides two concurrent feedforward paths from the front endvoltage sensing and matching amplification circuit to the combiningcircuit (as shown by the dotted arrows). The gain ratio of the twofeedforward paths can be kept unchanged if the parameters of the firstgain enhancement circuit comprising of transistor (M2), resistor (R2)and second gain enhancement circuit comprising of transistor (M3),resistor (R3) are given the same values in the absence of resistor (R8).However, the gain enhancement circuits contribute additional noise aswell. Therefore using the same parameters for both the first gainenhancement circuit and the second gain enhancement circuit may notalways be the optimal choice in terms of overall noise performance. Theanalysis can be shown below. In addition, the low noise amplifiercircuit with gain circuit as shown in FIG. 2 can be shown to achieve again-enhancement factor of gm₃R₃ when compared with the architecturewithout the gain circuit as shown in prior art publication “Wide-bandCMOS Low-Noise Amplifier Exploiting Thermal Noise Canceling”, FedericoBruccoleri et. al, IEEE Journal of Solid-State Circuits, Vol. 39, No. 2,Feb. 2004.

The analysis is as follows:

The gain A_(v,2) of the output common-source stage or combining circuit(M4 and M5) with output noise cancellation isA _(v,2)=1+R _(f) /R _(s)  (1)This relationship has been stated in prior art publication “Wide-bandCMOS Low-Noise Amplifier Exploiting Thermal Noise Canceling”, FedericoBruccoleri et. al, IEEE Journal of Solid-State Circuits, Vol. 39, No. 2,Feb. 2004 and serves as a reference for comparison for the enhanced gainof the low noise amplifier circuit as shown in FIG. 2. At node C of FIG.2, the noise voltage due to the first gain enhancement circuit (M3 andR3) can be expressed asV ² _(n,c)=4 kT·(NEF·g _(m3)+1/R ₃)R ₃ ² ·Δf  (2)WhereNoise excess factor (NEF)=γ·g_(ds0)/g_(m), (g_(ds0) is the channelconductance when V_(Ds)=0) (for submicron MOSFETs, NEF is well above 1)Δf is the calculation bandwidth.Practically, NEF·g_(m3)>>1/R₃. In addition, the case where noise perunit bandwidth is also considered.Thus, equation (2) can be simplified asV ² _(n,c)=4 kT·NEF·g _(m3) R ₃ ²  (3)Similarly, at node D, the noise voltage due to second gain enhancementcircuit (M2 and R2) can be expressed asV ² _(n,d)=4 kT·NEF·g _(m2) R ₂ ²  (4)The two noise voltages are uncorrelated. They can not be canceled bysubsequent combining circuit.Refer to the output node Vout, the noise due to first gain-enhancementcircuit and second gain enhancement circuit isV ² _(n,out)=4 kT·NEF·(g _(m2) R ₂ ² g _(m4) ² /g _(m5) ² +g _(m3) R ₃²).  (5)Equation (5) shows that the noise contribution of the second gainenhancement circuit (M2 and R2) is more significant than that of thefirst gain enhancement circuit (M3 and R3).The output noise of matching device M1 can be canceled by properlydesigning of the gain in the two feedforward paths.In FIG. 2, the cancellation condition is given byR _(s) ·g _(m2) R ₂ ·g _(m4) /g _(m5)=(R _(f) +R _(s))·g _(m3) R ₃.  (6)

Therefore, equation (5) becomesV ² _(n,out)=α·(g _(m3) R ₃)²[(1+R _(f) /R _(s))² /g _(m2)+1/g_(m3)]  (7)

where α=4kT·NEF.

From equation (7), the noise contribution of gain-enhancement circuitcan be minimized wheng _(m2) /g _(m3)=(1+R _(f) /R _(s))²  (8)

And the minimum output noise voltage isV ² _(n,out)=2·α·g _(m3) R ₃ ²  (9)Note that equations (7) to (9) are obtained under the noise cancellationcondition for the input matching amplifier circuit.From equation (8), the condition in equation (6) can be simplified asg _(m5) /g _(m4) =R ₂ /R ₃(1+R _(f) /R _(s)).  (10)Consider the overall small-signal gain, we have

$\begin{matrix}\begin{matrix}{A_{V} = {{{A_{v,1} \cdot g_{m\; 3}}R_{3}} + {g_{m\; 2}{R_{2} \cdot {g_{m\; 4}/g_{m\; 5}}}}}} \\{= {{( {A_{v,1} + 1 + {R_{f}/R_{s}}} ) \cdot g_{m\; 3}}R_{3}}}\end{matrix} & (11)\end{matrix}$

where A_(v,1) is the gain of input matching amplifier circuit,A _(v,1)=(g _(m1) R _(f)−1)R ₁ /R _(f) +R ₁.  (12)The result is a gain-enhancement factor g_(m3)R₃ when compared with thearchitecture in prior art publication “Wide-band CMOS Low-NoiseAmplifier Exploiting Thermal Noise Canceling”, Federico Bruccoleri et.al, IEEE Journal of Solid-State Circuits, Vol. 39, No. 2, Feb. 2004whose gain is (A_(v,1)+1+R_(f)/R_(s)).

FIG. 3 shows a graph of simulated performance of scattering parameters(S11, S21) versus frequency (F) and noise figure (NF) versus frequency(F) based on the architecture of the low noise amplifier according toFIG. 2. 2 pF capacitors are used for input and output coupling. Asimulated performance with noise figure of about 2.4 to 2.8 dB, gain(S21) of about 12 to 15.6 dB and input matching S11<−10 dB are achievedat a frequency range of between about 3.1 to 10.6 GHz. With basicconsiderations of parasitic capacitances, the −3 dB bandwidth is about1.5 to 9 GHz. The whole circuit draws only about 10.8 mA of current withlow supply voltage of about 1.2V.

Conventional inductor-peaking techniques can be applied to thearchitecture of FIG. 2 to further widen the −3-dB bandwidth beyond10.6-GHz. However, excessive silicon area will be consumed by the largepassive components. Therefore, an inductorless approach using capacitivepeaking is exploited. FIG. 4 shows a schematic of a capacitive-peakingcommon-source circuit. It is adopted from the source degenerationarchitecture. The capacitive-peaking common-source circuit 122 comprisesof a transistor, a resistor R_(L), a resistor R_(p) and a capacitorC_(p).

The gain of this circuit 122 can be written asA _(v) =−R _(L)/1/g _(m) +R _(p) |C _(p) =−R _(L)/1/g _(m)+1/1/R _(p)+jωC _(s)  (13)For the first order, C_(p) provides an increased A_(v) regardingfrequency. This effect can be understood conceptually from the resistivedegeneration architecture. It is well known that a source-degenerativeresistor R_(p) degrades gain and improves linearity while capacitorC_(p) provides a signal path in parallel with R_(p) to a groundconnection. At high frequencies, the path through C_(p) has lowimpedance. Thus, the resistive degeneration effect is degraded by C_(p)with the increasing frequency, resulting in an increasing gaincharacteristic.

FIG. 5 shows a circuit level representation of the architecture of thelow noise amplifier with capacitive-peaking according to an embodimentof the present invention. The capacitive-peaking circuits 122 areimplemented in the first gain enhancement circuit, the second gainenhancement circuit and the combining circuit respectively. Thesecapacitive-peaking circuits 122 are highlighted in dotted boxes.

The capacitive-peaking circuit 122 implemented in the first gainenhancement circuit results in an additional capacitor (C_(p3)) andresistor (R_(p3)) in FIG. 5 when compared to the circuit in FIG. 2. Thecapacitor (C_(p3)) comprises two ends, a first end is coupled to a firstend of the resistor (R_(p3)) and a second end is coupled to a second endof the resistor (R_(p3)). The first end of the capacitor (C_(p3)) andthe first end of the resistor (R_(p3)) is coupled to a capacitor (C2)and a resistor (R2). The second end of the capacitor (C_(p3)) and thesecond end of the resistor (R_(p3)) is coupled to the source terminal ofthe transistor (M3).

The capacitive-peaking circuit 122 implemented in the second gainenhancement circuit results in an additional capacitor (C_(p2)) andresistor (R_(p2)) in FIG. 5 when compared to the circuit in FIG. 2. Thecapacitor (C_(p2)) comprises two ends, a first end is coupled to a firstend of the resistor (R_(p2)) and a second end is coupled to a second endof the resistor (R_(p2)). The first end of the capacitor (C_(p2)) andthe first end of the resistor (R_(p2)) is coupled to a groundconnection. The second end of the capacitor (C_(p2)) and the second endof the resistor (R_(p2)) is coupled to the source terminal of thetransistor (M2).

The capacitive-peaking circuit 122 implemented in the combining circuitresults in an additional capacitor (C_(p4)) and resistor (R_(p4)) inFIG. 5 when compared to the circuit in FIG. 2. The capacitor (C_(p4))comprises two ends, a first end is coupled to a first end of theresistor (R_(p4)) and a second end is coupled to a second end of theresistor (R_(p4)). The first end of the capacitor (C_(p4)) and the firstend of the resistor (R_(p4)) is coupled to a ground connection. Thesecond end of the capacitor (C_(p4)) and the second end of the resistor(R_(p4)) is coupled to the source terminal of the transistor (M4). Thecapacitive-peaking circuit implemented in the combining circuit alsoresults in an additional resistor (R5) in FIG. 5 when compared to thecircuit in FIG. 2.

FIG. 6A shows a graph of simulated performance of voltage gain (Av)versus frequency (F) of a common-source circuit with capacitive-peakingbased on calculated gain according to equation (13) as statedpreviously. In FIG. 6A, the parameters are as follows: gm=20 mS,R_(L)=100Ω, R_(p)=10Ω, C_(p)=2 pF. From FIG. 6A, it can be seen that thepeaking is clear, which compensates for the high frequency gain drop dueto parasitic capacitances.

FIG. 6B shows a graph of simulated performance of voltage gain (Av)versus frequency (F) of a common-source circuit with and withoutcapacitive-peaking based on actual circuit implementation as shown inFIG. 2 and FIG. 5 respectively. In FIG. 6B, the parameters are set to bethe same as in FIG. 6A. The parameters are as follows: gm=20 mS,R_(L)=100Ω, R_(p)=10Ω, C_(p)=2 pF. From FIG. 6B, clear gain peaking isobserved. At low frequencies, around 3-dB gain degradation is foundbetween the plot with capacitive-peaking and the plot withoutcapacitive-peaking, which exhibits the effect of resistor degeneration.

Experimental Results

The efficiency of the new low noise amplifier circuit was verified byexperimental results of the fabricated integrated circuit (IC) chip. Thelow noise amplifier circuit was fabricated in a two-poly eight-metal0.13 μm triple-well CMOS technology. The cut off frequency F_(T) of NMOStransistor is over 90 GHz.

FIG. 7 shows a die microphotograph 124 of a fabricated low noiseamplifier chip according to an embodiment of the present invention. Asthe passive devices used are only resistors and capacitors, the lownoise amplifier chip with test pad occupies an area of only about 415μm×415 μm, which is relatively small.

The measurement of the LNA chip is performed on wafer using CascadeG-S-G RF probes. FIG. 8 shows a graph of simulated and measuredperformance of power gain (S₂₁) and input return loss (S₁₁) versusfrequency according to an embodiment of the present invention. S₂₁ isequivalent to the voltage or current gain of the amplifier. Similarly,the magnitude of the square of S₂₁ is equal to the power gain. Thesimulated maximum power gain is approximately 12.5 dB and the −3 dBbandwidth is approximately 3 to 11.7 GHz. The measured maximum powergain is approximately 11 dB and the −3 dB bandwidth is approximately 2to 9.6 GHz. The frequency dependent difference when comparing themeasured power gain to the simulated power gain is most likely due tothe extra parasitic capacitances in the real chip. Measurement showsthat the LNA only draws about 12.65 mA from a low supply voltage ofabout 1.5 V. The simulated input return loss is approximately −10 dBover 2 to 8 GHz. The measured input return loss is less than −9 dB over2.8 to 12 GHz, which shows the resistive shunt feedback, can effectivelyoffer a 50Ω matching resistance over the UWB frequencies.

FIG. 9 shows a graph of simulated and measured performance of noisefigure versus frequency according to an embodiment of the presentinvention. FIG. 9 shows that the simulated noise figure is approximately2.8 to 3.6 dB over a frequency range of approximately 2 to 9.6 GHz. FIG.9 also shows that the measured noise figure is higher at approximately3.6 to 4.8 dB over the same frequency range. Therefore the average noisefigure over a frequency range of approximately 2 to 9.6 GHz isapproximately 4 dB.

The aforementioned description of the various embodiments has beenpresented for purposes of illustration and description. It is notintended to be exhaustive or to limit the invention to the precise formdisclosed, and obviously many modifications and variations are possiblein light of the disclosed teaching. It is intended that the scope of theinvention be defined by the claims appended hereto.

1. A low noise amplifier circuit, comprising a front end voltage sensingand matching amplification circuit having an input and two outputs, thefront end voltage sensing and matching amplification circuit providing amatched signal at each output; a gain circuit having two inputs, eachinput being respectively coupled to at least one of the two outputs ofthe front end voltage sensing and matching amplification circuit, thegain circuit further having two outputs, an output signal being providedat each output of the gain circuit; and a combining circuit combiningthe two output signals of the gain circuit, the combining circuit havingtwo inputs, each input being respectively coupled to at least one of thetwo outputs of the gain circuit, the combining circuit furthercomprising an output providing a combined signal; wherein the gaincircuit comprising a first gain enhancement circuit having an inputcoupled to a first output of the front end voltage sensing and matchingamplification circuit and an output coupled to a first input of thecombining circuit; a second gain enhancement circuit coupled to thefirst gain enhancement circuit and having an input coupled to a secondoutput of the front end voltage sensing and matching amplificationcircuit and an output coupled to a second input of the combiningcircuit; and a virtual ground circuit connected between the first gainenhancement circuit and the second gain enhancement circuit on one sideand a reference potential on the other side; the first gain enhancementcircuit and the second gain enhancement circuit having a common currentpath and being configured to provide two concurrent feedforward paths tothe combining circuit.
 2. The low noise amplifier circuit of claim 1,further comprising an alternating current coupling circuit having aninput coupled to the first output of the front end voltage sensing andmatching amplification circuit and an output coupled to the input of thefirst gain enhancement circuit.
 3. The low noise amplifier circuit ofclaim 2, the alternating current coupling circuit further comprising acapacitive element and a resistive element.
 4. The low noise amplifiercircuit of claim 1, further comprising a current enhancement circuitconnected between the first gain enhancement circuit and the second gainenhancement circuit, the current enhancement circuit providingadditional current to the second gain enhancement circuit.
 5. The lownoise amplifier circuit of claim 4, the current enhancement circuitfurther being connected to the virtual ground circuit.
 6. The low noiseamplifier circuit of claim 5, the current enhancement circuit comprisinga resistive element.
 7. The low noise amplifier circuit of claim 1, thevirtual ground circuit comprising a capacitive element, a first terminalof which being connected to the first gain enhancement circuit and thesecond gain enhancement circuit and a second terminal of which beingconnected to the reference potential.
 8. The low noise amplifier circuitof claim 1, the front end voltage sensing and matching amplificationcircuit comprising a voltage sensing amplifier circuit and a matchingamplifier circuit.
 9. The low noise amplifier circuit of claim 8, thevoltage sensing amplifier circuit comprising an input and an output, theoutput being coupled to an input of the second gain enhancement circuit.10. The low noise amplifier circuit of claim 8, the voltage sensingamplifier circuit comprising a feedback resistor and a source resistorsensing the voltage applied to the input of the voltage sensingamplifier circuit.
 11. The low noise amplifier circuit of claim 8, thematching amplifier circuit comprising an input and an output beingcoupled to the first gain enhancement circuit.
 12. The low noiseamplifier circuit of claim 8, the matching amplifier circuit comprisingthe feedback resistor, a resistive element and a transistor providingthe source resistor matching.
 13. The low noise amplifier circuit ofclaim 1, the first gain enhancement circuit comprising a transistor anda resistive element.
 14. The low noise amplifier circuit of claim 1, thesecond gain enhancement circuit comprising a transistor and a resistiveelement.
 15. The low noise amplifier circuit of claim 1, the combiningcircuit comprising two serially coupled transistors.
 16. The low noiseamplifier circuit of claim 1, further comprising a first capacitorpeaking circuit connected between the first gain enhancement circuit andthe second gain enhancement circuit.
 17. The low noise amplifier circuitof claim 16, the first capacitor peaking circuit comprising a capacitiveelement and a resistive element.
 18. The low noise amplifier circuit ofclaim 1, further comprising a second capacitor peaking circuit connectedbetween the second gain enhancement circuit and a reference potential.19. The low noise amplifier circuit of claim 18, the second capacitorpeaking circuit comprising a capacitive element and a resistive element.20. The low noise amplifier circuit of claim 1, further comprising athird capacitor peaking circuit connected between the combining circuitand a reference potential.
 21. The low noise amplifier circuit of claim20, the third capacitor peaking circuit comprising a capacitive elementand a resistive element.
 22. A gain circuit in a low noise amplifier,the gain circuit comprising: a first gain enhancement circuit having aninput coupled to a first output of a front end voltage sensing andmatching amplification circuit and having an output; a second gainenhancement circuit coupled to the first gain enhancement circuit andhaving an input coupled to a second output of the front end voltagesensing and matching amplification circuit and having an output; and avirtual ground circuit connected between the first gain enhancementcircuit and the second gain enhancement circuit on one side and areference potential on the other side; the first gain enhancementcircuit and the second gain enhancement circuit having a common currentpath and being configured to provide two concurrent feedforward paths toa combining circuit.